Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The process of implementing a circuit design on a programmable IC often involves verifying whether or not the circuit design meets timing requirements. The timing requirements may be specified in terms of a maximum clock frequency at which the implemented circuit may operate. In some instances, a failure of a circuit to comply with timing requirements may not be discovered until the circuit design has been placed and routed. Critical paths, which are the paths of the circuit design that do not satisfy timing constraints, may be identified through use of various design tools. However, fixing critical paths may be problematic in instances in which each critical path is made of many nets. The challenge is compounded in a complex design that might have many critical paths.